Star Plan process war: TSMC, Samsung, and Intel's technology routes diverge

As Moore's Law approaches its physical limit, the competition among the three major semiconductor giants in the world has entered a white-hot stage in the 2nm process node. Each of them adopts a different transistor architecture to break through the performance bottleneck. 2025 will be a key year for the commercialization of 2nm technology. The following is the latest progress and technology comparison of the three major manufacturers:

1. Star Plan: Turn to Star Plan transistor architecture, mass production in 2025

Technological breakthrough:

Abandon FinFET, adopt GAA (surround gate) Nanosheet structure, improve gate control capability by stacking silicon nanosheets (3~5 layers), and reduce leakage rate by 30%.

Integrate CoWoS-L advanced packaging, support 12 HBM4 memory stacking, and target AI chip needs.

Star Plan mass production plan:

Risk trial production in the second half of 2025, mass production in 2026, the first wave of customers include Apple, Star Plan, and AMD.

2nm performance is 10-15% higher than 3nm, and power consumption is reduced by 25-30%.